I. Field of the Invention
This invention relates to junction type field effect transistors.
II. Description of the Prior Art
Junction type field effect transistors (hereinafter referred to as J-FETs) are also called unipolar transistors and have various features which distinguish them from common bipolar transistors. The greatest of these features is high input impedance, which makes them very suitable for use as an impedance conversion circuit device. On the other hand, when used as an amplifier device, J-FETs have the disadvantage of being low in gain. The gain of a J-FET is expressed in terms of the mutual conductance thereof, which is proportional to the ratio of gate width, W, to gate length, L. Accordingly, a J-FET having a high gain will be obtained if the ratio W/L is increased. In order to increase the ratio W/L, L must be decreased and W must be increased. However, L has a lower limit by reason of the problem of processing accuracy as well as the fact that excessively small values for L cause the inherent pentode characteristics of the J-FET to approximate triode characteristics, so that a gate region having all the greater value for W is required. The formation of such an elongated gate region is difficult in the prior art, thus resulting in a lower yield of the products and a greater cost of production.
FIG. 1 schematically illustrates a sectional view of a prior art N-channel J-FET chip. In this figure, reference numeral 1 designates a P-type semiconductor body used as a gate region, on which an N-type epitaxial layer 2 is formed. In epitaxial layer 2 are formed an upper gate region 3, a drain region 4, and a source region 5 as well as an isolation region 6 for isolating these operational regions into an island-like form and connecting upper gate region 3 to lower gate region 1. A channel 7 is to be formed between upper gate region 3 and lower gate region 1. On epitaxial layer 2, a source electrode 8, a drain electrode 9, and an oxide film 10 serving for surface passivation are formed.
In the above-described structure, the peripheral length of the P-N junction of upper gate region 3 is so great that minor defects become very likely to be created with the result that such defects may impair the P-N junction. Moreover, if ionic contaminants are introduced into oxide film 10 formed on upper gate region 3 and isolation region 6, the surfaces of these regions may create a faulty channel and thereby develop an electrical short circuit. Furthermore, if mobile ions such as sodium ions are present in oxide film 10, the leak current at the boundaries between the aforesaid regions 3, 6 and the corresponding oxide layer 10 will increase with time and result in unsatisfactory reliability.